The present invention relates to a semiconductor device and particularly relates to a high withstand voltage semiconductor device produced from a semiconductor material (hereinafter referred to wide bandgap semiconductor) having a wider bandgap than that of silicon.
Wide bandgap semiconductors such as silicon carbide (hereinafter referred to as SiC), gallium nitride (hereinafter referred to as GaN), etc. have recently attracted a great deal of attention as semiconductor materials for power semiconductor devices. The wide bandgap semiconductors potentially break the characteristic limit of silicon which is a conventional semiconductor material. On the other hand, SiC or GaN has a disadvantage that it is very difficult to form P-type regions by an ion injection method. Although it has been reported that SiC turned p type when aluminum (Al) or gallium (Ga) ions were injected into SiC at a high temperature, it is impossible to form sufficient p-type regions because resistance is very high. That is, it is difficult for the wide bandgap semiconductor to form p-type regions selectively in an n-type substrate. For this reason, it is very difficult to provide a guard ring in a peripheral voltage withstanding structure portion surrounding an active region portion in which a drift current flows.
Therefore, a bevel structure is known as a peripheral voltage withstanding structure of a semiconductor device (hereinafter referred to as wide bandgap semiconductor device) formed of a wide bandgap semiconductor. Incidentally, in this specification and accompanying drawings, each technical term showing a layer or region and headed by “n” or “p” means that electrons or positive holes are majority carriers. Each superscript “+” or “−” given to “n” or “p” means that the concentration of an impurity is higher or lower than the concentration of the impurity in a layer or region described without any superscript.
FIG. 13 is a sectional view showing the configuration of a peripheral voltage withstanding structure portion of a bevel structure in an MOSFET (insulated gate field effect transistor). As shown in FIG. 13, the peripheral voltage withstanding structure portion 1 has a structure (bevel structure) in which an element edge side portion (right half part in FIG. 13) of p and p+ layers 3 and 4 epitaxially grown on an n− layer 2 has been removed by dry etching. In this structure, a large leak current flows if a depletion layer comes in contact with a dicing side surface 5 when a high withstand voltage is applied between a source and a drain. To prevent the large leak current from flowing, an n+ region 6 is provided in the element edge portion so that the depletion layer can be restrained from being stretched.
A structure in which an element edge side end surface of a p-type layer is provided as an inclined surface (e.g. see JP-A-2002-185015 and its corresponding International Application WO 02/49114 A2) is also commonly known as a structure similar to the aforementioned structure. A structure in which trenches surrounding an active region portion are formed so that a p+ layer is provided between the bottom of each trench and the trench (e.g. see JP-A-11-87698) is further commonly known as another peripheral voltage withstanding structure.
The peripheral voltage withstanding structure disclosed in JP-A-2002-185015, however, has the following problems. Firstly, since the element withstand voltage depends on the taper angle of the inclined surface, high controllability is required of the dry etching. Secondly, it is necessary to prevent the inclined surface and the surface of the n− layer from being damaged by the dry etching. Because of these requirements, it is difficult to produce a semiconductor device having a desired element withstand voltage at a good yield rate. Moreover, it is difficult to obtain sufficiently high reliability for a long term. Thirdly, it is necessary to provide the n+ region in the element edge portion. Fourthly, the length of the peripheral voltage withstanding structure portion becomes large, that is, the length from a boundary between the active region portion and the peripheral voltage withstanding structure portion to the dicing side surface becomes large. Since there is no current flowing in the peripheral voltage withstanding structure portion, it is preferable that the length of the peripheral voltage withstanding structure portion is made as short as possible to thereby increase the area of the active region portion to improve efficiency of the whole element.